A hybrid test compression technique for efficient testing of systems-on-a-chip
نویسنده
چکیده
One of the major challenges in testing a System-on-a-Chip (SOC) is dealing with the large test data size. To reduce the volume of test data, several efficient test data compression techniques have been recently proposed. In this paper, we propose hybrid test compression techniques that combine the Geometric-Primitives-Based compression technique with the frequency-directed run-length (FDR) and extended frequencydirected run-length (EFDR) coding techniques. Based on experimental results, we demonstrate the effectiveness of the proposed hybrid compression techniques in increasing the test data compression ratios over those obtained by the GeometricPrimitives-Based compression technique.
منابع مشابه
A Geometric-Primitives-Based Compression Scheme for Testing Systems-on-a-Chip
The increasing complexity of systems-on-a-chip with the accompanied increase in their test data size has made the need for test data reduction imperative. In this paper, we introduce a novel and very efficient lossless compression technique for testing systems-on-a-chip based on geometric shapes. The technique exploits reordering of test vectors to minimize the number of shapes needed to encode...
متن کاملAn Efficient Test Relaxation Technique for Combinational & Full-Scan Sequential Circuits
Reducing test data size is one of the major challenges in testing systems-on-a-chip. This problem can be solved by test compaction and/or compression techniques. Having a partially specified or relaxed test set increases the effectiveness of test compaction and compression techniques. In this paper, we propose a novel and efficient test relaxation technique for combinational and full-scan seque...
متن کاملImplementation of VlSI Based Image Compression Approach on Reconfigurable Computing System - A Survey
Image data require huge amounts of disk space and large bandwidths for transmission. Hence, imagecompression is necessary to reduce the amount of data required to represent a digital image. Thereforean efficient technique for image compression is highly pushed to demand. Although, lots of compressiontechniques are available, but the technique which is faster, memory efficient and simple, surely...
متن کاملDesign of a novel congestion-aware communication mechanism for wireless NoC architecture in multicore systems
Hybrid Wireless Network-on-Chip (WNoC) architecture is emerged as a scalable communication structure to mitigate the deficits of traditional NOC architecture for the future Multi-core systems. The hybrid WNoC architecture provides energy efficient, high data rate and flexible communications for NoC architectures. In these architectures, each wireless router is shared by a set of processing core...
متن کاملAn Efficient Test Relaxation Technique for Combinational Circuits Based on Critical Path Tracing
Reducing test data size is one of the major challenges in testing systems-on-a-chip. This can be achieved by test compaction and/or compression techniques. Having a partially specified or relaxed test set increases the effectiveness of compaction and compression techniques. In this paper, we propose a novel and efficient test relaxation technique for combinational circuits. It is based on criti...
متن کامل